Inside PCI Express 6.0: A Bandwidth Leap Through PAM4 Modulation

Bandwidth demands between processors, memory, and accelerators are climbing sharply as compute models grow larger. PCI Express 6.0 answers by doubling the previous generation's speed to 64 GT/s per lane.

From NRZ to PAM4

Earlier generations raised speed the straightforward way: by doubling the signal frequency. That approach ran into a physical wall — at higher frequencies, the copper traces on a circuit board lose too much signal energy.

PAM4 takes another route. Instead of two voltage levels representing zero and one, it uses four levels, each carrying two bits. Data rates double without raising the frequency, so signal attenuation does not get any worse.

The cost of four voltage levels

Packing four levels into the same voltage range shrinks the spacing between them to a third. Noise that once meant nothing is now enough to turn one level into its neighbour, and the bit error rate jumps by several orders of magnitude.

That makes forward error correction mandatory rather than optional. FEC adds redundant data so the receiver can correct errors without asking for a retransmission — and a retransmission would wreck latency on an interconnect like this.

A tight latency budget

FEC always adds latency, because the receiver has to collect a full block of data before it can check it. On a long-distance network, a few extra microseconds go unnoticed; on a bus connecting a processor to memory, that overhead would defeat the entire purpose.

The specification therefore sets an FEC latency budget below 2 nanoseconds — a figure that forces far simpler error-correcting codes than those used in storage or networking. The fixed-size FLIT scheme was chosen precisely to meet that limit.

Who actually needs it

For personal computing, PCIe 6.0 brings no noticeable benefit yet; even consumer graphics cards do not saturate previous-generation lanes. The real gains are in the data center, in accelerator clusters that have to exchange gradients in large volumes between nodes.

That is where the interconnect becomes the deciding factor, and this standard becomes the backbone that keeps added accelerators from immediately hitting a memory transfer bottleneck.